CS271 Spring 2002 Midterm I Sample Questions

 

 

1. Assume we have a 4 instruction program that contains a loop. Further assume that a trace of the actual execution of this program reveals the following instruction execution sequence: 1, 2, 3, 1, 2, 3, 1, 2, 3, 4. Assume each instruction takes 1 word of memory, and that main memory access time is 100ns.  Further assume we can ignore the time it takes for all parts of instruction execution other than instruction fetch.

a)      How long with the above 10 instruction trace take to execute from main memory?

100+100+100+100+100+100+100+100+100+100 = 1000 ns

b)     Designers are considering adding a cache to the design. Assume the cache has a 10 ns access time, and that the cache is initially empty. How long will the above sequence take?

100+100+100+10+10+10+10+10+10+100 = 460 ns

c)      For part b, what is the cache hit ratio on the sample instruction trace?

6/10 = .60 = 60%

 

2. a) Chapter 2 prob 1.             

               5+10+5 = 20 ns => 50 MIPS

    b) Assume a 3 stage pipeline (load ALU, ALU Execute, Store result), and ignore instruction fetch time Ð now what is the MIPS for this design?

               10 ns worst case pipeline stage => 100 MIPS

 

3. Consider a code with two valid codewords: 111    000

a)      What is the hamming distance of the above code?

a.       3

b)      Can it detect a 1 bit error?

a.       Yes

c)      Can it correct a 1 bit error?

a.       Yes

d)      Can it detect a two bit error?

a.       Yes ( same as 2 one bit errors)

e)      Can it correct a two bit error?

a.       No.

 

4. Show the truth table for a two bit decrement by 1 Input is a two bit number plus a carry in, output is a two bit result plus a carry out. (i.e., f(11,0) = 10, carry 0))

(Note Ð in the below I1 is the high order bit, reverse of solution in class)

                  

I1

I0

Cin

O1

O0

Cout

0

0

0

1

1

1

0

0

1

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

1

0

0

0

1

0

1

0

1

0

0

0

1

1

0

1

0

0

1

1

1

0

1

0

 

    b) write the logic formula for the high order output bit given the input (I0, I1, and Carry in)

               !I1!I0!Cin + !I1!I0Cin + !I1I0Cin + I1I0!Cin

 

5. Write the Boolean expression for the C output of Chapter 3 problem 12.

!( !(A !(AB)) !(B !(AB)))

 

    b) Simplify if you can, naming the transformation rule used in each step.

               ! ( (!A+AB)(!B+AB)) DeMorgan

               (!(!A+AB) + !(!B+AB)) DeMorgan

               A!(AB) + B!(AB) DeMorgan

               A(!A+!B) + B(!A+!B) DeMorgan

               A!A+A!B + B!A +B!B Distributive

               A!B+B!A Inverse Law

               Exclusive or!

              

 

7. a 32 bit wide bus does one transfer in 100ns. How many MB/sec (megabytes/sec) can it transfer?

               (32/8*106)/(100*10-9)

 

8. Chapter 3 #26.

Yes, as discussed in class

 

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